1. Field of the Invention
The present invention relates to packaging substrates and fabrication methods thereof, and more particularly, to a packaging substrate having an embedded interposer and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products tend to have reduced size, high performance, multi-function and high speed. FIG. 1 is a schematic cross-sectional view of a conventional flip-chip packaging structure.
Referring to FIG. 1, a bismaleimide-triazine (BT) packaging substrate 10 is provided. The packaging substrate 10 has a core layer 102 and opposite first and second surfaces 10a, 10b. A plurality of flip-chip bonding pads 100 are formed on the first surface 10a of the packaging substrate 10 and electrically connected to the electrode pads 120 of a semiconductor chip 12 through a plurality of solder bumps 11. An underfill 17 is filled between the first surface 10a of the packaging substrate 10 and the semiconductor chip 12 for encapsulating the solder bumps 11. Further, a plurality of solder ball bonding pads 101 are formed on the second surface 10b of the packaging substrate 10 such that solder balls 13 can be mounted on the solder ball bonding pads 101 for electrically connecting an external electronic device such as a printed circuit board (not shown).
Since the semiconductor chip 12 is fabricated below 45 nm node, a dielectric material having an extreme low k (ELK) or an ultra low k (ULK) is usually used in a back end of the line (BEOL) of the semiconductor chip 12. However, such a low-k dielectric material is porous and brittle. Therefore, during a thermal cycling test for reliability characterization of the flip chip package, the solder bumps 11 can easily crack due to uneven thermal stresses caused by a big difference between the thermal expansion coefficients (CIEs) of the packaging substrate 10 and the semiconductor chip 12, thereby easily causing the semiconductor chip 12 to crack and hence reducing the product reliability.
Further, in order to obtain electronic products having reduced size and improved functions, the semiconductor chip 12 tends to have a high density of nano-scale circuits so as to have reduced pitches between the electrode pads 120. On the other hand, the flip-chip bonding pads 100 of the packaging substrate 10 are only of micro-scale pitches. Hence, the packaging substrate 10 is not suitable for the high-density nano-scale circuits of the semiconductor chip 12, thereby adversely affecting the fabrication of electronic products having reduced size and improved functions.
Therefore, there is a need to provide a packaging substrate and a fabrication method thereof so as to overcome the above-described drawbacks.